The present invention relates to a latching comparator and, in particular, to a latching comparator having an input offset adjustment.
Successive approximation and flash analog-to-digital (A/D) converters have historically used some type of latching comparator and frequently incorporate some method of nulling the comparator's input-referred offset voltage. Input-referred offset adjustment capability is particularly important for maintaining accuracy in flash A/D converters. A single latching comparator can be combined with an N-bit D/A converter and with additional logic to form an N-bit successive-approximation A/D converter, or can be arrayed 2.sup.N times to form an N-bit flash A/D converter.
A typical method of nulling input-referred offset involves measuring and storing the offset voltage on a sampling capacitor and then inserting the capacitor in series with the signal path. This method requires specialized circuitry and a certain sequence of operations such that the measured voltage exactly cancels the offset voltage of the comparator. A difficulty with this method is that the sampling capacitor results in a higher comparator input capacitance due to parasitic coupling of the sampling capacitor to the integrated circuit substrate on which the comparator is fabricated. Also, the sampling capacitor and the specialized track/hold and offset cancellation circuitry consume a relatively large area on the integrated circuit.